The present invention generally relates to superconducting circuits having Josephson devices, and more particularly to a superconducting circuit that includes an output conversion circuit for converting an output of the superconducting circuit to a signal suitable for use in a semiconductor processor.
Superconducting circuits that use the Josephson devices generally produce output logic signals with a logic amplitude determined by the gap energy pertinent to the material used for the Josephson junction. When using niobium (Nb), a typical material for the Josephson junction, for this purpose, a logic amplitude of about 3 mV is obtained. Although this small logic amplitude may be advantageous for reducing the power consumption, this level of logic amplitude is too small for driving the semiconductor circuits that operate in the room temperature environment. It should be noted that the Josephson circuits require an extremely low temperature environment for operation, and for this purpose, a low temperature vessel containing the cooling medium such as liquid helium, is used for accommodating the Josephson circuits. Thus, a processing circuit operating at the room temperature environment is essential for taking over and processing the output of Josephson processors. Generally, a logic amplitude of about several hundred millivolts is necessary for such a processing circuit. For example, when a CMOS device is used for this purpose, the necessary logic amplitude for driving the CMOS device is about 1.5 volts. When using a GaAs FET, on the other hand, the preferred logic amplitude is about 800 mV. When a bipolar transistor is used, the preferred logic amplitude is about 400 mV.
Thus, when the Josephson processor supplies the output directly to these semiconductor processing circuits, the semiconductor processing circuits may not operate properly or at all. Even when operated properly, such a system is extremely vulnerable to external noises. Thus, there is an acute demand for a superconducting output driver that is capable to operating in the low temperature environment together with the Josephson processor as a part of the Josephson integrated circuit for converting the logic amplitude of the Josephson processor to a level suitable for processing by the semiconductor circuits.
FIG. 1 shows a conventional superconducting output driver 10 proposed in the Japanese Laid-open Patent Application No. 61-171551. Referring to FIG. 1, the circuit comprises a first junction group 11 including a plurality of Josephson junctions J11, J12, . . . ,J1n connected in series, a second junction group 12 including a plurality of Josephson junctions J21, J22, . . . , a first resistant R1 connected in series to the first junction group 11, and a second resistance R2 identical with the first resistance R1 and connected in series to the second junction group 12, wherein the junction group 11 and the resistance R1 form a first branch of a bridge circuit, and the junction group 12 and the resistance R2 form a second branch of the bridge circuit. The driver 10 is injected with a drive current Ib at a terminal PVcc connected to a neutral node of the bridge, and the Josephson junctions in the junction groups 11 and 12 have a critical current Is that is identical in each Josephson junction.
In operation, the bias current Ib supplied at the terminal PVcc is divided and caused to flow through the first and second branches with a magnitude identical in the first and second branches. Thus, a current Ib/2 flows through the first and second branches. As long as the current Ib/2 is smaller than the critical current of the Josephson junctions included in the branch, the junction groups 11 and 12 maintain the superconducting state.
When an input current Iin is supplied in this state to an input terminal Pin connected to a node between the junction group 11 and the resistance R1, the current Iin is caused to flow through a path indicated in FIG. 1 by a dotted line, and a current with the magnitude of Iin/2+Ib/2 is caused to flow through the second branch while a current with the magnitude of -Iin/2+Ib/2 flows through the first branch. Thus, when the magnitude Iin/2+Ib/2 in the second branch exceeds the critical current of at least some of the Josephson junctions in the second junction group 12, these Josephson junctions experience a transition to the finite voltage state and there appears a resistance in the second branch. In response to the appearance of the resistance, the drive current Ib/2 hitherto flowing through the second branch is now diverted to the first branch. Thereby, an overshoot of the current Ib flowing through the first junction group 11 occurs and the Josephson junctions J11-J1n in the first group 11 are all switched to the finite voltage state. Further, in response to the switching of the Josephson junctions J11-J1n, all the Josephson junctions J21-J2n are switched to the finite voltage state and a voltage corresponding to the number of stages of the Josephson junctions multiplied by the energy gap of each Josephson junction appears at an output terminal Pout connected to the node between the resistance R2 and the second junction group 12.
FIGS. 2(A)-2(F) show the above described operation wherein FIG. 2(A) defines the parameters in the circuit of FIG. 1 and FIGS. 2(B)-2(F) are waveforms appearing in correspondence to the foregoing operations.
With the rise of the input current Iin at the input terminal Pin as shown in FIG. 2(B), the current IR flowing through the second branch increases and some of the Josephson junctions start to switch to the finite voltage state with a timing designated as T1. After the timing T1, the current IR drops sharply while the current IL flowing through the first branch experiences a surge at a time T2 as shown in FIG. 2(D). In correspondence to the surge in the current IL, the current IR1 flowing through the first resistance R1 expererinces a corresponding maximum as shown in FIG. 2(E). In response to the surge of the current IL, all the Josephson junctions in the first branch cause the switching to the finite voltage state and the current IR again increases as shown in a large peak at the timing T3 as shown in FIG. 2(B). Thereby, all the Josephson junctions in the second branch experience the switching to the finite voltage state and the output voltage corresponding to the gap voltage multiplied by the number of series-connected Josephson junctions appear at the output terminal Pout. In correspondence to this, the output current IRL to a load RLD increases as shown in FIG. 2(F).
In this conventional driver, however, there exits a problem, when a semiconductor processing circuit is connected to the output terminal Pout, such that the current IL or IR supposed to cause the switching of the Josephson junctions is diverted to the semiconductor circuit forming the load RLD because of the low input impedance of the semiconductor circuits. It should be noted that such a loss of the current in the bridge circuit at the time T2 or T3 corresponding to the transition of the Josephson junctions causes an operational instability of the output driver. Further, there is another problem, caused by the large number of Josephson junctions connected in series, such that the expected overshoot of the current at the time T2 or T3 may not occur with sufficient magnitude when there is a large number of Josephson junctions and corresponding large but unpredictable parasitic inductance in the first and second branches. Thus, the conventional circuit of FIG. 1 has suffered from a problem of insufficient reliability.